In semiconductor design, a semiconductor intellectual property core or block (IP core or IP block) is a reusable unit of logic, cell, or chip layout design. The trend in the semiconductor industry, and this includes IP blocks, is that the devices have become smaller and smaller, and more and more complex and dense. Since the full verification of a complex IP block is almost impossible, the trend is to design IP blocks such that they are configurable. This is especially true for IP blocks that include analog components or have only analog components, as the presence of analog components makes verifying the IP block even more difficult.
This leads to the design of “glue logic,” where “glue logic” is custom electronic circuitry which is needed to achieve compatible interfaces between two devices. With regard to IP blocks, glue logic enables a user to reconfigure the IP in the final device to avoid respins. In current technology nodes like 90 nm and 65 nm, the area overhead is not too much of a concern with regard to the glue logic, but the power the glue logic consumes is a major issue.
A good example of IP which has heavy configuration requirements is a serializer/deserializer (SerDes) which is a pair of functional blocks commonly used in high speed communications. The blocks convert data between serial data and parallel interfaces in each direction. One reason why configuration requirements are high with regard to a SerDes is the fact that a SerDes is intended to support different protocols. Another reason relates to the adjustment capabilities of the analog portion of a SerDes as well as the I/O's.
One SerDes example with heavy configuration requirements is LSI's 90 nm SerDes targeting PCI-Express/SAS/FC protocol (expansion card interface technology). Such SerDes actually has about 650 configuration input signals. Another SerDes which targets SONET/SDH SerDes (fiber optic interface technology) and proprietary backplane applications has internal registers (controlled by an advanced high-performance bus (AHB)) which number about 700. This is just the register overhead itself, but there is always some control logic necessary to program these registers, like AHB IF or an external processor (e.g., Intel 8051). This control logic can add an additional 700-1000 registers. Taking a factor of 10-15 for a register/gate equivalent, the additional gates which are required number in the range of 20,000. (One configuration module which currently exists is even more extreme and has 57,780 gates (master)). If one assumes that such a SerDes will be used 16 to 32 times on a customer design, the gate count of the configuration registers can easily rise up to 600,000 and above.
With smaller technology, the leakage power consumption become more dominant than the dynamic power, especially since there exists good techniques to address dynamic power reduction (e.g., clock gating). The assumption is that for configuration registers as described above, the clock gating approach should be very effective. However, the leakage portion of the power consumption still exists and dominates the total power consumption.